전자부품 데이터시트 검색엔진 |
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GS72116AT-7I 데이터시트(PDF) 7 Page - GSI Technology |
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GS72116AT-7I 데이터시트(HTML) 7 Page - GSI Technology |
7 / 18 page Rev: 1.04a 10/2002 7/18 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS72116ATP/J/T/U AC Characteristics * These parameters are sampled and are not 100% tested. Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL Read Cycle Parameter Symbol -7 -8 -10 -12 Unit Min Max Min Max Min Max Min Max Read cycle time tRC 7— 8 — 10 — 12 — ns Address access time tAA —7 — 8 — 10 — 12 ns Chip enable access time (CE)tAC —7 — 8 — 10 — 12 ns Byte enable access time (UB, LB)tAB —3 — 3.5 — 4 — 5ns Output enable to output valid (OE)tOE —3 — 3.5 — 4 — 5ns Output hold from address change tOH 3— 3 — 3 — 3 — ns Chip enable to output in low Z (CE) tLZ* 3— 3 — 3 — 3 — ns Output enable to output in low Z (OE) tOLZ* 0— 0 — 0 — 0 — ns Byte enable to output in low Z (UB, LB) tBLZ* 0— 0 — 0 — 0 — ns Chip disable to output in High Z (CE) tHZ* —3.5 — 4 — 5 — 6ns Output disable to output in High Z (OE) tOHZ* —3 — 3.5 — 4 — 5ns Byte disable to output in High Z (UB, LB) tBHZ* —3 — 3.5 — 4 — 5ns tAA tOH tRC Address Data Out Previous Data Data valid |
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