74AC11898

10BIT PARALLELOUT SERIAL SHIFT REGISTER

SCAS143 − OCTOBER 1990 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

2−2

logic diagram (positive logic)

SRG10

13

18

20

1

2

3

8

17

A

14

B

C1/

19

9

10

11

12

&

1D

QA

QB

QC

QD

QE

QF

QG

QH

QI

QJ

CLR

CLK

QJ

12

QI

QH

11

10

QG

QF

QE

9

8

3

QD

QC

QB

QA

2

1

20

19

CLR

CLK

B

A

18

13

14

17

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.