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SN74ABTH16460DL 데이터시트(PDF) 2 Page - Texas Instruments

부품명 SN74ABTH16460DL
상세설명  4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS
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SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable
(LEB1–LEB4, LEBA, and LEAB1–LEAB4) and clock/clock-enable (CLK/CLKEN) inputs are used to control data
storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don’t care as long
as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from
low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned
high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the
low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the
clock is a don’t care.
Four select pins (SEL0, SEL1, CE_SEL0, and CE_SEL1) are provided to multiplex data (A port), or to select
one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH16460 is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74ABTH16460 is characterized for operation from –40
°C to 85°C.
Function Tables
A-TO-B OUTPUT ENABLE†
INPUTS
OUTPUT
OEB
OEBn
Bn
H
H
Z
H
LZ
L
HZ
L
L
Active
† n = 1, 2, 3, 4
A-TO-B STORAGE
(assuming OEB = L, OEBn = L)‡
INPUTS
OUTPUTS
CLKENAB
CE_SEL1
CE_SEL0
CLKAB
LEAB1
LEAB2
LEAB3
LEAB4
B1
B2
B3
B4
X
X
X
H or L
H
L
L
L
A
A0
A0
A0
X
X
X
H or L
H
H
H
L
A
AA
A0
L
X
X
L
LLLL
A0
A0
A0
A0
L
LL
LLLL
A
A0
A0
A0
L
LH
LLLL
A0
AA0
A0
L
HL
LLLL
A0
A0
AA0
L
HH
LLLL
A0
A0
A0
A
H
X
X
L
L
L
L
A0
A0
A0
A0
‡ This table does not cover all the latch-enable cases since they have similar results.


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