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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SN74GTLPH306 데이터시트(PDF) 4 Page - Texas Instruments |
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SN74GTLPH306 데이터시트(HTML) 4 Page - Texas Instruments |
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4 / 17 page  www.ti.com Recommended Operating Conditions (1) (2) (3) (4) SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER SCES284E – OCTOBER 1999 – REVISED APRIL 2005 MIN NOM MAX UNIT VCC Supply voltage 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 VTT Termination voltage V GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 VREF Reference voltage V GTLP 0.87 1 1.1 B port VTT VI Input voltage V Except B port VCC 5.5 B port VREF + 0.05 VIH High-level input voltage V Except B port 2 B port VREF – 0.05 VIL Low-level input voltage V Except B port 0.8 IIK Input clamp current –18 mA IOH High-level output current A port –24 mA A port 24 IOL Low-level output current mA B port 50 ∆t/∆v Input transition rise or fall rate Outputs enabled 10 ns/V ∆t/∆V CC Power-up ramp rate 20 µs/V TA Operating free-air temperature –40 85 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. (3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. (4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. 4 |
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유사한 설명 - SN74GTLPH306_15 |
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