DAC6573IPW datasheet(5/35 Pages) TI1

부품명	DAC6573IPW

상세설명	QUAD, 10-Bit, LOW-POWER, VOLTAGE OUTPUT,INTERFACE DIGITAL-TO-ANALOG CONVERTER

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DAC6573

SLAS402 – NOVEMBER 2003

TIMING CHARACTERISTICS (continued)

V

DD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Standard mode

300

ns

Fast mode

20 + 0.1CB

300

ns

tFCL

Fall time of SCL signal

High-speed mode, CB = 100 pF max

10

40

ns

High-speed mode, CB = 400 pF max

20

80

ns

Standard mode

1000

ns

Fast mode

20 + 0.1CB

300

ns

tRDA

Rise time of SDA signal

High-speed mode, CB = 100 pF max

10

80

ns

High-speed mode, CB = 400 pF max

20

160

ns

Standard mode

300

ns

Fast mode

20 + 0.1CB

300

ns

tFDA

Fall time of SDA signal

High-speed mode, CB = 100 pF max

10

80

ns

High-speed mode, CB = 400 pF max

20

160

ns

Standard mode

4.0

µs

Setup time for STOP

tSU; tSTO

Fast mode

600

ns

condition

High-speed mode

160

ns

Capacitive load for SDA and

CB

400

pF

SCL

Fast mode

50

ns

Pulse width of spike

tSP

suppressed

High-speed mode

10

ns

Noise margin at the HIGH

Standard mode

level for each connected

Fast mode

VNH

0.2 VDD

V

device (including

High-speed mode

hysteresis)

Noise margin at the LOW

Standard mode

level for each connected

Fast mode

VNL

0.1 VDD

V

device (including

High-speed mode

hysteresis)

5

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