전자부품 데이터시트 검색엔진 |
|
CD74ACT297 데이터시트(PDF) 1 Page - Texas Instruments |
|
CD74ACT297 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 18 page CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297D – AUGUST 1998 – REVISED JUNE 2002 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption D Digital Design Avoids Analog Compensation Errors D Easily Cascadable for Higher-Order Loops D Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) D Dynamically Variable Bandwidth D Very Narrow Bandwidth Attainable D Power-On Reset D Output Capability – Standard: XORPD OUT, ECPD OUT – Bus Driver: I/D OUT D SCR Latch-Up-Resistant CMOS Process and Circuit Design D Balanced Propagation Delays D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 description/ordering information The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as shown in Figure 1. Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops. The length of the up/down K counter is digitally programmable according to the K-counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A, B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs can maximize the overall performance of the digital phase-locked loop. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING 55 °Cto125°C SOIC M Tube CD74ACT297M ACT297M –55 °C to 125°C SOIC – M Tape and reel CD74ACT297M96 ACT297M † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 B A ENCTR K CLK I/D CLK D/U I/D OUT GND VCC C D φA2 ECPD OUT XORPD OUT φB φA1 M PACKAGE (TOP VIEW) |
유사한 부품 번호 - CD74ACT297_14 |
|
유사한 설명 - CD74ACT297_14 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |