CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

4

POST OFFICE BOX 655303

recommended operating conditions (see Note 4)

MIN

TYP

MAX

UNIT

Supply voltage, VDDQ, AVDD

2.3

2.7

V

Low level input voltage VIL

CLK, CLK, FBIN, FBIN

VDDQ/2 – 0.18

V

Low level input voltage, VIL

PWRDWN

–0.3

0.7

V

High level input voltage VIH

CLK, CLK, FBIN, FBIN

VDDQ/2 + 0.18

V

High level input voltage, VIH

PWRDWN

1.7

VDDQ + 0.3

V

DC input signal voltage (see Note 5)

–0.3

VDDQ

V

Differential input signal voltage VID (see Note 6)

DC

CLK, FBIN

0.36

VDDQ + 0.6

V

Differential input signal voltage, VID (see Note 6)

AC

CLK, FBIN

0.7

VDDQ + 0.6

V

Output differential cross-voltage, VOX (see Note 7)

VDDQ/2 – 0.2 VDDQ/2

VDDQ/2 + 0.2

V

Input differential pair cross-voltage, VIX (see Note 7)

VDDQ/2 – 0.2

VDDQ/2 + 0.2

V

High-level output current, IOH

–12

mA

Low-level output current, IOL

12

mA

Input slew rate, SR

1

4

V/ns

Operating free-air temperature, TA

0

85

°C

NOTES:

4. Unused inputs must be held high or low to prevent them from floating.

5. DC input signal voltage specifies the allowable dc execution of differential input.

6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level

and VCP is the complementary input level.

7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be

crossing.