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AD7997BRUZ-03 데이터시트(PDF) 4 Page - Analog Devices |
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AD7997BRUZ-03 데이터시트(HTML) 4 Page - Analog Devices |
4 / 32 page AD7997/AD7998 Rev. 0 | Page 4 of 32 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, VINL 0.8 V max VDD = 5 V 0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD Input Capacitance, CIN3 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ± 1 µA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See the Modes of Operation section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ fSCL = 100 kHz 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ fSCL = 400 kHz 147 kSPS typ fSCL = 3.4 MHz, 188 kSPS typ @ 5 V POWER REQUIREMENTS VDD 2.7/5.5 V min/max IDD Digital inputs = 0 V or VDD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Mode 3 (I2C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V Power Dissipation Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Power Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V 1 Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-Mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the Terminology section. 3 Guaranteed by initial characterization. |
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