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LM25119Q 데이터시트(PDF) 4 Page - Texas Instruments

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부품명 LM25119Q
상세설명  Wide Input Range, Dual Synchronous Buck Controller
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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LM25119, LM25119-Q1
SNVS680H – AUGUST 2010 – REVISED MAY 2016
www.ti.com
Product Folder Links: LM25119
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
14
RES
O
The restart timer pin for an external capacitor that configures the hiccup mode current limiting. A
capacitor on the RES pin determines the time the controller remains off before automatically
restarting in hiccup mode. The two regulator channels operate independently. One channel may
operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode
commences when either channel experiences 256 consecutive PWM cycles with cycle-by-cycle
current limiting. After this occurs, a 10-µA current source charges the RES pin capacitor to the 1.25-V
threshold which restarts the overloaded channel.
15
COMP2
O
Output of the channel2 internal error amplifier. The loop compensation network must be connected
between this pin and the FB2 pin.
16
FB2
I
Feedback input and inverting input of the channel2 internal error amplifier. A resistor divider from the
channel2 output to this pin sets the output voltage level. The regulation threshold at the FB2 pin is
0.8 V.
17
DEMB
I
Logic input that enables diode emulation when in the low state. In diode emulation mode, the low-
side MOSFET is latched off for the remainder of the PWM cycle when the buck inductor current
reverses direction (current flow from output to ground). When DEMB is high, diode emulation is
disabled allowing current to flow in either direction through the low-side MOSFET. A 50-k
Ω pulldown
resistor internal to the LM25119 holds DEMB pin low and enables diode emulation if the pin is left
floating.
18
SS2
I
An external capacitor and an internal 10-µA current source set the ramp rate of the channel2 error
amp reference. The SS2 pin is held low when VCC1 or VCC2 < 4 V, UVLO < 1.25 V or during
thermal shutdown.
19
RAMP2
I
PWM ramp signal. An external resistor and capacitor connected between the SW2 pin, the RAMP2
pin and the AGND pin sets the channel2 PWM ramp slope. Proper selection of component values
produces a RAMP2 signal that emulates the current in the buck inductor.
20
CS2
I
Current sense amplifier input. Connect to the high side of the channel2 current sense resistor.
21
CSG2
I
Kelvin ground connection to the external current sense resistor. Connect directly to the low side of
the channel2 current sense resistor.
22
PGND2
G
Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the
channel2 current sense resistor.
23
LO2
O
Low-side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous
MOSFET through a short, low inductance path.
24
VCC2
P
Bias supply pin. Locally decouple to PGND2 using a low ESR or ESL capacitor located as close to
controller as possible.
25
SW2
I/O
Switching node of the buck regulator. Connect to channel2 bootstrap capacitor, the source terminal of
the high-side MOSFET and the drain terminal of the low-side MOSFET.
26
HO2
O
High-side MOSFET gate drive output. Connect to the gate of the channel2 high-side MOSFET
through a short, low inductance path.
27
HB2
P
High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel2 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the
high-side MOSFET gate and must be placed as close to the controller as possible.
28
UVLO
I
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the
shutdown mode with all function disabled. If the UVLO pin is greater than 0.4 V and below 1.25 V, the
regulator is in standby mode with the VCC regulators operational, the SS pins grounded and no
switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25 V, the SS pins are
allowed to ramp and pulse width modulated gate drive signals are delivered at the LO and HO pins. A
20-µA current source is enabled when UVLO exceeds 1.25 V and flows through the external UVLO
resistors to provide hysteresis.
29
VIN
P
Supply voltage input source for the VCC regulators.
30
HB1
P
High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel1 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the
high-side MOSFET gate and must be placed as close to controller as possible.
31
HO1
O
High-side MOSFET gate drive output. Connect to the gate of the channel1 high-side MOSFET
through a short, low inductance path.
32
SW1
I/O
Switching node of the buck regulator. Connect to channel1 bootstrap capacitor, the source terminal of
the high-side MOSFET and the drain terminal of the low-side MOSFET.
EP
EP
Exposed pad of WQFN package. No internal electrical connections. Solder to the ground plane to
reduce thermal resistance.


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