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SN74ABT833DW 데이터시트(PDF) 3 Page - Texas Instruments |
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SN74ABT833DW 데이터시트(HTML) 3 Page - Texas Instruments |
3 / 13 page SN54ABT833, SN74ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) ERR CLR OEA OEB 8 8 8 8 8 9 P MUX 1 1 1 G1 1 2k 1D R C1 EN EN 8x 8x A1–A8 CLK PARITY B1–B8 15 10 14 1 13 11 2–9 16–23 Pin numbers shown are for the DW, JT, and NT packages. ERROR-FLAG FUNCTION TABLE INPUTS INTERNAL TO DEVICE OUTPUT PRE-STATE OUTPUT ERR FUNCTION CLR CLK POINT P ERRn–1† ERR H ↑ H H H H ↑ X LL Sample H ↑ L XL L X X X H Clear † The state of ERR before any changes at CLR, CLK, or point P |
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