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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM3550 데이터시트(PDF) 4 Page - Texas Instruments |
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LM3550 데이터시트(HTML) 4 Page - Texas Instruments |
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4 / 37 page  LM3550 SNVS569B – MAY 2009 – REVISED MAY 2013 www.ti.com Electrical Characteristics (1) (2) Limits in standard typeface are for TJ = +25°C. Limits in boldface type apply over the full ambient junction temperature range ( −30°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to the LM3550 Typical Application Circuit with: : VIN = 3.6V, CIN = 4.7µF, COUT = 2.2µF, C1 = C2 = 1 µF. Symbol Parameter Conditions Min(3) Typ Max(3) Units 54 60 66 2.7V ≤ VIN ≤ 5.5V ILED− Current Sink Accuracy 90 100 110 mA 3.0V ≤ VOUT ≤ 5.5V 180 200 220 Going into 5.3 5.479 OVP VOVP Output Over Voltage Protection 2.7V ≤ VIN ≤ 5.5V V Hysteresis 0.2 4.275 4.5 4.666 2.7V ≤ VIN ≤ 5.5V VOUT Output Voltage Regulation 4.75 5 5.169 V IOUT = 0 mA 5.035 5.3 5.479 VBAL BAL Pin Voltage Regulation 2.7V ≤ VIN ≤ 5.5V VOUT / 2 V 2.7V ≤ VIN ≤ 5.5V IIND IND Pin Current Regulation 3.3 4.8 6.3 mA VIND = 2.0V fSW Switching Frequency 2.7V ≤ VIN ≤ 5.5V 0.882 1 1.153 MHz Feedback Pin Regulation 2.7V ≤ VIN ≤ 5.5V VFB 94 100 106 mV Voltage VOUT = 4.6V ALD/TEMP Pin Reference VALD/TEMP 2.7V ≤ VIN ≤ 5.5V 0.95 1 1.05 V Voltage VEOC EOC Pin Output Logic Low ILOAD = 3 mA 400 mV IIN-CL Input Current Limit VOUT = 0V 534 610 mA Device Disabled ISD Shutdown Supply Current 1.8 4 µA 2.7V ≤ VIN ≤ 5.5V 2.7V ≤ VIN ≤ 5.5V IOUT = 0 mA IQ Quiescent Supply Current 168 240 µA 5V Charge Mode Non-Switching High 1.23 VIN VSTROBE Strobe Logic Thresholds 2.7V ≤ VIN ≤ 5.5V V Low 0 0.7 I2C-Compatible Voltage Specifications (SCL, SDA) VIL Input Logic Low 2.7V ≤ VIN ≤ 5.5V 0 0.7 V VIH Input Logic High 2.7V ≤ VIN ≤ 5.5V 1.23 VIN V VOL Output Logic Low ILOAD = 3 mA 400 mV I2C-Compatible Timing Specifications (SCL, SDA) t1 SCL (Clock Period) 294 ns Data In Setup Time to SCL t2 fSCL = 400 kHz. 100 ns High t3 Data Out Stable After SCL Low fSCL = 400 kHz. 0 ns SDA Low Setup Time to SCL t4 fSCL = 400 kHz. 100 ns Low (Start) SDA High Hold Time After SCL t5 fSCL = 400 kHz. 100 ns High (Stop) (1) All voltages are with respect to the potential at the GND pin. (2) Junction-to-ambient thermal resistance ( θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. (3) Min and Max limits are specified by design, test, or statistical analysis. Typical (typ.) numbers are not ensured, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25ºC. 4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM3550 |
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