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74AVC16835DGGRG4 데이터시트(PDF) 1 Page - Texas Instruments

부품명 74AVC16835DGGRG4
상세설명  18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
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SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
 Family
D DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
Operation
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description
A Dynamic Output Control (DOC
) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC
)
Circuitry Technology and Applications, literature number SCEA009.
136
–128
–144
–160
0.4
0.8
1.2
1.6
2.0
2.4
2.8
170
153
119
102
85
68
51
34
17
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
TA = 25°C
Process = Nominal
IOL – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
TA = 25°C
Process = Nominal
IOH – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
–80
–96
–112
–32
–48
–64
0
–16
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low
logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE
is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright
 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC and Widebus are trademarks of Texas Instruments.


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