FPGA

GTL2014PW

LVTTL

GTL

Chipset

VTT

R

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DIR

B0

B1

VREF

B2

B3

GND

GND

A3

A2

GND

A1

A0

VCC

3.3 V

Port_A to Port_B

LVTTL to GTL

3.3 V

GND

1.0 V

3.3 V

75

Not Avaliable

Not Avaliable

VCC

Vref

VTT

DIR

R

R1

R2

SN74GTL2014

www.ti.com

SCLS746A – FEBRUARY 2014 – REVISED OCTOBER 2014

Typical Application (continued)

9.2.2 LVTTL/TTL to GTL–/GTL/GTL+

Because GTL is an open-drain interface, the selection of pullup resistor depends on the application requirement

(for example, data rate) and PCB trace capacitance.

Figure 7. Application Diagram for LVTTL to GTL

9.2.2.1 Design Requirements

The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in the Application

Information section show standard voltage level and typical resistor values.

NOTE

Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.

9.2.2.2 Detailed Design Procedure

To begin the design process, determine the following:

1. Select direction based upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).

2. Set up appropriate DIR pin and VREF/VTT.

3. Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to

GTL–/GTL/GTL+).

Copyright © 2014, Texas Instruments Incorporated

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