전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SN74V245-15PAGEP 데이터시트(PDF) 1 Page - Texas Instruments

Click here to check the latest version.
부품명 SN74V245-15PAGEP
상세설명  DSP-SYNC FIRST-IN, FIRST-OUT MEMORY
Download  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

SN74V245-15PAGEP 데이터시트(HTML) 1 Page - Texas Instruments

  SN74V245-15PAGEP Datasheet HTML 1Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 2Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 3Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 4Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 5Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 6Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 7Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 8Page - Texas Instruments SN74V245-15PAGEP Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 42 page
background image
SN74V245-EP
www.ti.com
SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013
4096 × 18 DSP-SYNC™ FIRST-IN, FIRST-OUT MEMORY
Check for Samples: SN74V245-EP
1
FEATURES
2
4096 × 18-Bit Organization Array
Provide a DSP Glueless Interface to Texas
Instruments TMS320™ DSPs
7.5-ns Read and Write Cycle Time
Packaged in 64-Pin Thin Quad Flat Package
3.3-V VCC, 5-V Input Tolerant
First-Word or Standard Fall-Through Timing
SUPPORTS DEFENSE, AEROSPACE,
Single or Double Register-Buffered Empty and
AND MEDICAL APPLICATIONS
Full Flags
Controlled Baseline
Easily Expandable in Depth and Width
One Assembly and Test Site
Asynchronous or Coincident Read and Write
One Fabrication Site
Clocks
Available in Military (–55°C to 125°C)
Asynchronous or Synchronous Programmable
Temperature Range
Almost-Empty and Almost-Full Flags With
Extended Product Life Cycle
Default Settings
Extended Product-Change Notification
Half-Full Flag Capability
Product Traceability
Output Enable Puts Output Data Bus in High-
Impedance State
High-Performance Submicron CMOS
Technology
DSP and Microprocessor Interface Control
Logic
DESCRIPTION/ORDERING INFORMATION
The SN74V245 is a very high-speed, low-power CMOS clocked first-in first-out (FIFO) memory. It supports clock
frequencies up to 133 MHz and has read-access times as fast as 5 ns. This DSP-Sync FIFO memory features
read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front
end (AFE) buffering, network, video, and data communications.
The SN74V245 is a synchronous FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between DSPs,
microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE) input controls the
3-state output.
The synchronous FIFO has two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR), and
two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the programmable
flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A half-full flag (HF) is
available when the FIFO is used in a single-device configuration.
Two timing modes of operation are possible with the SN74V245: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN and enabling a rising
RCLK edge, shifts the word from internal memory to the data output lines.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
DSP-SYNC, TMS320 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


유사한 부품 번호 - SN74V245-15PAGEP

제조업체부품명데이터시트상세설명
logo
Texas Instruments
SN74V245-15PAG TI-SN74V245-15PAG Datasheet
590Kb / 43P
[Old version datasheet]   512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SN74V245-15PAG TI-SN74V245-15PAG Datasheet
600Kb / 43P
[Old version datasheet]   512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
More results

유사한 설명 - SN74V245-15PAGEP

제조업체부품명데이터시트상세설명
logo
List of Unclassifed Man...
TDC1030 ETC1-TDC1030 Datasheet
226Kb / 14P
   FIRST-IN FIRST-OUT MEMORY
logo
Texas Instruments
SN74ACT7882-20FN TI1-SN74ACT7882-20FN Datasheet
254Kb / 18P
[Old version datasheet]   CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ABT3611 TI1-SN74ABT3611_05 Datasheet
459Kb / 29P
[Old version datasheet]   CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ALS233B TI1-SN74ALS233B_16 Datasheet
752Kb / 18P
[Old version datasheet]   ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SN74ALS2232A TI1-SN74ALS2232A Datasheet
130Kb / 9P
[Old version datasheet]   ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SN74ABT3612 TI1-SN74ABT3612_15 Datasheet
521Kb / 34P
[Old version datasheet]   CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ACT7801 TI1-SN74ACT7801 Datasheet
279Kb / 19P
[Old version datasheet]   1024x18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
logo
Fairchild Semiconductor
74F403A FAIRCHILD-74F403A Datasheet
167Kb / 15P
   First-In First-Out (FIFO) Buffer Memory
logo
Integrated Device Techn...
7201LA20TP IDT-7201LA20TP Datasheet
313Kb / 14P
   First-In/First-Out dual-port memory
7201LA35J IDT-7201LA35J Datasheet
313Kb / 14P
   First-In/First-Out dual-port memory
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com