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SN74V245-15PAGEP 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74V245-15PAGEP 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 42 page SN74V245-EP www.ti.com SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013 4096 × 18 DSP-SYNC™ FIRST-IN, FIRST-OUT MEMORY Check for Samples: SN74V245-EP 1 FEATURES 2 • 4096 × 18-Bit Organization Array • Provide a DSP Glueless Interface to Texas Instruments TMS320™ DSPs • 7.5-ns Read and Write Cycle Time • Packaged in 64-Pin Thin Quad Flat Package • 3.3-V VCC, 5-V Input Tolerant • First-Word or Standard Fall-Through Timing SUPPORTS DEFENSE, AEROSPACE, • Single or Double Register-Buffered Empty and AND MEDICAL APPLICATIONS Full Flags • Controlled Baseline • Easily Expandable in Depth and Width • One Assembly and Test Site • Asynchronous or Coincident Read and Write • One Fabrication Site Clocks • Available in Military (–55°C to 125°C) • Asynchronous or Synchronous Programmable Temperature Range Almost-Empty and Almost-Full Flags With • Extended Product Life Cycle Default Settings • Extended Product-Change Notification • Half-Full Flag Capability • Product Traceability • Output Enable Puts Output Data Bus in High- Impedance State • High-Performance Submicron CMOS Technology • DSP and Microprocessor Interface Control Logic DESCRIPTION/ORDERING INFORMATION The SN74V245 is a very high-speed, low-power CMOS clocked first-in first-out (FIFO) memory. It supports clock frequencies up to 133 MHz and has read-access times as fast as 5 ns. This DSP-Sync FIFO memory features read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data communications. The SN74V245 is a synchronous FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE) input controls the 3-state output. The synchronous FIFO has two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR), and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A half-full flag (HF) is available when the FIFO is used in a single-device configuration. Two timing modes of operation are possible with the SN74V245: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 DSP-SYNC, TMS320 are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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