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TL16C450 데이터시트(PDF) 4 Page - Texas Instruments |
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TL16C450 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 27 page TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS037C − MARCH 1988 − REVISED JANUARY 2006 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO.† I/O DESCRIPTION A0 A1 A2 31 30 29 I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description. ADS 28 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in the state they were in when the low-to-high transition of ADS occurred. BAUDOUT 17 O Baud out. BAUDOUT is a16 × clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input. CS0 CS1 CS2 14 15 16 I Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the ADS signal description. CSOUT 27 O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select inputs (CS0, CS1, and CS2). CSOUT is low when the chip is deselected. CTS 40 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an interrupt is generated. D0 − D7 2 − 9 I/O Data bus. D0 − D7 are 3-state data lines that provide a bidirectional path for data, control, and status information between the ACE and the CPU. DCD 42 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes state, an interrupt is generated. DDIS 26 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can disable an external transceiver. DISTR DISTR 25 24 I Data input strobes. When either DISTR or DISTR is active (high or low respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation. The other input should be tied in its inactive state (i.e., DISTR tied low or DISTR tied high). DOSTR DOSTR 21 20 I Data output strobes. When either DOSTR or DOSTR is active (high or low respectively), while the ACE is selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation. The other input should be tied in its inactive state (i.e., DOSTR tied low or DOSTR tied high). DSR 41 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed state since the last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state, an interrupt is generated. DTR 37 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level. DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing bit 0 (DTR) of the modem control register. INTRPT 33 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. The four conditions that cause an interrupt are: a receiver error, received data is available, the transmitter holding register is empty, or an enabled modem status interrupt. The INTRPT output is reset (inactivated) either when the interrupt is serviced or as a result of a master reset. MR 39 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer to Table 2 for ACE reset functions. † Terminal numbers shown are for the FN package. |
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