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TLC1518IDW 데이터시트(PDF) 11 Page - Texas Instruments |
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TLC1518IDW 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 39 page TLC1514, TLC1518 5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS252 – DECEMBER 1999 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 read cycle (read FIFO or read CFR) (continued) FIFO read cycle The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read command. The first FIFO content is output immediately before the command is decoded. If this command is not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is because the read cycle does not generate EOC or INT nor does it carry out any conversion. SCLK CS FS SDI INT EOC SDO ID15 ID14 ID13 ID12 ID14 OD6 OD5 OD3 OD0 12 3 4 5 6 711 12 15 16 1 10 OD9 OD8 OD7 ID15 OD4 Command FIFO Data Figure 4. TLC1514/TLC1518 Continuous FIFO Read Cycle (FS = 1) (controlled by SCLK, SCLK can stop between each 16 SCLKs) |
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