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TDA6651TT 데이터시트(PDF) 9 Page - NXP Semiconductors |
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TDA6651TT 데이터시트(HTML) 9 Page - NXP Semiconductors |
9 / 55 page 2004 Mar 22 9 Philips Semiconductors Product specification 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) TDA6650TT; TDA6651TT 8.1 Write mode; R/W=0 After the address transmission (first byte), data bytes can be sent to the device (see Table 3). Five data bytes are needed to fully program the TDA6650TT; TDA6651TT. The I2C-bus transceiver has an auto-increment facility that permits programming the device within one single transmission (address + 5 data bytes). The TDA6650TT; TDA6651TT can also be partly programmed on the condition that the first data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The first bit of the first data byte transmitted indicates whether byte 2 (first bit = 0) or byte 4 (first bit = 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. The fractional calculator is updated only at the end of the transmission (STOP condition). Each control byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider data are valid only if no new I2C-bus transmission is started (START condition) during the computation period of 50 µs. Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in the same transmission. handbook, full pagewidth ADDRESS BYTE DIVIDER BYTE 1 START ADDRESS BYTE I2C transmission dedicated to another IC I2C transmission dedicated to the MOPLL START 50 µs DIVIDER BYTE 2 CONTROL BYTE 1 CONTROL BYTE 2 CONTROL BYTE 1 CONTROL BYTE 2 STOP FCE921 Fig.4 Example of I2C-bus transmission frame. Table 3 I2C-bus write data format Note 1. MSB is transmitted first. NAME BYTE BIT ACK MSB(1) LSB Address byte 1 1 1 0 0 0 MA1 MA0 R/W=0 A Divider byte 1 (DB1) 2 0 N14 N13 N12 N11 N10 N9 N8 A Divider byte 2 (DB2) 3 N7 N6 N5 N4 N3 N2 N1 N0 A Control byte 1 (CB1); see Table 4 4 1 T/A = 1 T2 T1 T0 R2 R1 R0 A 1 T/A = 0 0 0 ATC AL2 AL1 AL0 A Control byte 2 (CB2) 5 CP2 CP1 CP0 BS5 BS4 BS3 BS2 BS1 A |
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