UC1548

UC2548

UC3548

UDG-95038

20

100

1000

2000

100

1000

5000

C (pF)

500

50

500

Oscillator Frequency as a Function of CT

Frequency Decrease as a Function of RT

RT = Open

UDG-95039

The undervoltage lockout block diagram is shown in Fig-

ure 1. The VCC comparator monitors chip supply voltage.

Hysteretic thresholds are set at 13V and 10V to facilitate

off-line applications. If the VCC comparator is low, ICC is

low (<500

µA) and the output is low.

pair of resistors divides the input line to UV. Hysteretic in-

put line thresholds are programmed by Rv1 and Rv2. The

thresholds are

• (1 + Rv1/Rv2′) and

• (1 + Rv1/Rv2) where

Rv2

′ = Rv2||90k.

The resulting hysteresis is

• Rv1 / 90k.

µA) and

the output is low.

When both the UV and VCC comparators are high, the in-

ternal bias circuitry for the remainder of the chip is

activated. The CDC pin (see discussion on Maximum Duty

Cycle Control and Soft Start) and the Output are held low

until VREF exceeds the 4.5V threshold of the VREF com-

parator. When VREF is good, control of the output driver is

transferred to the PWM circuitry and CDC is allowed to

charge.

If any of the three UVLO comparators go low, the UVLO

latch is set, the output is held low, and CDC is discharged.

This state will be maintained until all three comparators are

high and the CDC pin is fully discharged.

UNDERVOLTAGE LOCKOUT

4