GS8182T19/37BD-435/400/375/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.03a 11/2011

7/27

© 2008, GSI Technology

FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

5X the value of the desired RAM output impedance at mid-rail. The allowable range of RQ to guarantee impedance matching

continuously is between 175

Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is

affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply

voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each

impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver

is implemented with discrete binary weighted impedance steps.

Common I/O SigmaDDR-II+ B2 SRAM Truth Table

LD

R/W

DQ

Operation

A + 0

A + 1

↑

1

X

Hi-Z

Hi-Z

Deselect

↑

0

0

Write

↑

0

1

Q@K(n+2) for A+0

Q@K(n+2 ) for

A+1

Read

Note:

Q is controlled by K clocks if C clocks are not used.