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TSB41LV06APZPG4 데이터시트(PDF) 4 Page - Texas Instruments

부품명 TSB41LV06APZPG4
상세설명  IEEE 1394b SIX-PORT CABLE TRANSCEIVER/ARBITER
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TSB41LV06A
IEEE 1394a SIXPORT CABLE TRANSCEIVER/ARBITER
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
When the PHY-LLC interface is in the low-power disabled state, the TSB41LV06A automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41LV06A disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when all ports are either disconnected, or disabled with the port’s
interrupt enable bit cleared. The TSB41LV06A exits the low-power mode when the LPS input is asserted high
or when a port event occurs which requires that the TSB41LV06A become active in order to respond to the event
or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes
active (and the PHY-LLC interface initializes and becomes operative) within 7.3 ms after LPS is asserted high
when the TSB41LV06A is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would
otherwise cause C/LKON to be active.


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