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GM71C17400C 데이터시트(PDF) 1 Page - Hynix Semiconductor |
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GM71C17400C 데이터시트(HTML) 1 Page - Hynix Semiconductor |
1 / 10 page GM71C(S)17400C/CL 4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM Description The GM71C(S)17400C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71C(S)17400C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)17400C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)17400C/CL to be packaged in a standard 300 mil 24(26) pin SOJ, and a standard 300 mil 24(26) pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply 5.0V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. Features * 4,194,304 Words x 4 Bit Organization * Fast Page Mode Capability * Single Power Supply (5.0V+/-10%) * Fast Access Time & Cycle Time * Low Power Active : 660/605/550mW (MAX) Standby : 11mW (CMOS level : MAX) : 0.83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 2048 Refresh Cycles/32ms * 2048 Refresh Cycles/128ms (L-version) * Battery backup operation (L-version) * Test function : 16bit parallel test mode (Unit: ns) GM71C(S)17400C/CL-5 GM71C(S)17400C/CL-6 GM71C(S)17400C/CL-7 tRAC tCAC tRC tPC 50 60 13 15 90 110 35 40 70 18 130 45 Pin Configuration 24(26) SOJ (Top View) VCC I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 24(26) TSOP II VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 Rev 0.1 / Apr’01 |
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