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MC100E310 데이터시트(PDF) 1 Page - ON Semiconductor |
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MC100E310 데이터시트(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 7 1 Publication Order Number: MC100E310/D MC100E310 5 V ECL Low Voltage 2:8 Differential Fanout Buffer Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 10−20 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 10−20 ps increase in TPD, so the relative skew between any two output pairs remains about 25 ns. For more information on using PECL, designers should refer to ON Semiconductor Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series Contains Temperature Compensation. Features • Dual Differential Fanout Buffers • 200 ps Part-to-Part Skew • 50 ps Output-to-Output Skew • 28-lead PLCC Packaging • Q Output will Default LOW with Inputs Open or at VEE • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input 50 kW Pulldown Resistors • ESD Protection: ♦ > 2 kV Human Body Model ♦ > 200 V Machine Model • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Level 3 (Pb-Free) (For Additional Information, see Application Note AND8003/D) • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 212 Devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package PLCC−28 FN SUFFIX CASE 776−02 www.onsemi.com *For additional marking information, refer to Application Note AND8002/D. MC100E310FNG AWLYYWW 128 ORDERING INFORMATION Device Package Shipping† MC100E310FNG PLCC−28 (Pb-Free) 37 Units / Tube MC100E310FNR2G 500 Tape & Reel PLCC−28 (Pb-Free) †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. |
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