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MC100EP91MNR2G 데이터시트(PDF) 1 Page - ON Semiconductor

부품명 MC100EP91MNR2G
상세설명  Any Level Positive Input to NECL Output Translator
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 6
1
Publication Order Number:
MC100EP91/D
MC100EP91
2.5 V/3.3 V Any Level
Positive Input to
-3.3 V/-5.5 V NECL
Output Translator
Description
The MC100EP91 is a triple any level positive input to NECL output
translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL,
CML or LVDS signals, and translates them to differential NECL
output signals (−3.0 V/−5.5 V).
To accomplish the level translation the EP91 requires three power
rails. The VCC pins should be connected to the positive power supply,
and the VEE pin should be connected to the negative power supply.
The GND pins are connected to the system ground plane. Both VEE
and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
Maximum Input Clock Frequency = > 2.0 GHz Typical
Maximum Input Data Rate = > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range:
VCC = 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
MARKING DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
SOIC−20 WB
DW SUFFIX
CASE 751D
1
20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb-Free Package
100
EP91
ALYWG
G
1
24
QFN−24
MN SUFFIX
CASE 485L
24
1
20
1
MC100EP91
AWLYYWWG
www.onsemi.com
(Note: Microdot may be in either location)
SOIC−20 WB
QFN−24
ORDERING INFORMATION
Device
Package
Shipping†
MC100EP91DWG
SOIC−20 WB
(Pb-Free)
38 Units / Tube
MC100EP91DWR2G
1000 Tape & Reel
QFN−24
(Pb-Free)
MC100EP91MNR2G
3000 Tape & Reel
MC100EP91MNG
92 Units / Tube
SOIC−20 WB
(Pb-Free)
QFN−24
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.


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