MC100LVELT23

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2

1

2

3

45

6

7

8

Q0

GND

Figure 1. 8-Lead Pinout (Top View)

and Logic Diagram

D0

Q1

D1

D1

D0

LVPECL

LVTTL

Table 1. PIN DESCRIPTION

Pin

Function

Q0, Q1

D0*, D1*

D0*, D1*

GND

EP

LVTTL Outputs

Differential LVPECL Inputs

Positive Supply

Ground

(DFN8 only) Thermal exposed pad must

be connected to a sufficient thermal con-

duit. Electrically connect to the most neg-

ative supply (GND) or leave unconnec-

ted, floating open.

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

50 kW

Internal Input Pullup Resistor

50 kW

ESD Protection

Human Body Model

Machine Model

CDM

> 1500 V

> 100 V

> 2000 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Pb-Free Pkg

SOIC−8 NB

TSSOP−8

DFN−8

Level 1

Level 3

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

91

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. Refer to Application Note AND8003/D for additional information.