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LM2631MTC-ADJ 데이터시트(PDF) 9 Page - National Semiconductor (TI) |
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LM2631MTC-ADJ 데이터시트(HTML) 9 Page - National Semiconductor (TI) |
9 / 12 page Design Procedure (Continued) current stress for the inductor and switch devices, and re- quires a bigger output capacitor for the same output voltage ripple requirement. A reasonable value is setting the ripple current to be 30% of the dc output current. Since the ripple current increase with the input voltage, the maximum input voltage is always used to determine the inductance. The dc resistance of the inductor is a key parameter for the effi- ciency. Lower dc resistance is available with a bigger wind- ing area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal to 2% of the out- put power. Input Capacitor A low ESR aluminum or tantalum capacitor is needed be- tween the drain of the high-side MOSFET and ground to pre- vent large voltage transients from appearing at the input. The capacitor is selected based on the RMS current and voltage requirements. The RMS current is given by: The RMS current reaches its maximum (I OUT/2) when VIN equals 2V OUT. A parallel of several capacitors may be re- quired to meet the RMS current rating. For an aluminum ca- pacitor, the voltage rating should be at least 25% higher than the maximum input voltage. If a tantalum capacitor is used, the voltage rating should be about twice the maximum input voltage. The tantalum capacitor should also be surge current tested by the manufacturer. It is also recommended to put a small ceramic capacitor (0.1 µF) between the V IN pin and ground. Output Capacitor The selection of C OUT is driven by the maximum allowable output voltage ripple. The output ripple in FPWM mode is ap- proximated by: The ESR term plays the dominant role in determining the voltage ripple. Low ESR aluminum electrolytic or tantalum capacitors (such as Nichicon PL series, Sanyo OS-CON, Sprague 593D, 594D, and AVX TPS) are recommended. Electrolytic capacitors are not recommended for temperature below −25˚C since their ESR rises dramatically at cold tem- perature. Tantalum capacitors have a much better ESR specification at cold temperatures and are preferred for low temperature applications. Power MOSFETs Two N-channel logic-level MOSFETs are required for this ap- plication. MOSFETs with low on-resistance and total gate charge are recommended to achieve high efficiency. The drain-source breakdown voltage ratings are recommended to be 1.2 times the maximum input voltage. Schottky Diode D 1 The Schottky diode D 1 is used to prevent the intrinsic body diode of the low-side MOSFET Q 2 from conducting during the dead time when both MOSFETs are off. Since the for- ward voltage of D 1 is less than the body diode, efficiency can be improved. The breakdown voltage rating of D 1 is pre- ferred to be 25% higher than the maximum input voltage. Since D 1 is only on for a short period of time (about 200 ns each cycle), the average current rating for D 1 only requires to be higher than 30% of the maximum output current. It is important to place D 1 very close to the drain and source of Q 2, extra parasitic inductance in the parallel loop will slow the turn-on of D 1 and direct the current through the body di- ode of Q 2. R 1 and R2 (Programming Output Voltage) Use the following formula to select the appropriate resistor values: V OUT = VREF(1+R1/R2) where V REF = 1.238V Select a value for R 2 between 10kΩ and 100kΩ. (Use 1% or higher accuracy metal film resistors). Current sense resistor The value of the sense resistor is determined by the mini- mum current limit voltage and the maximum peak current. It can be calculated as follows: where TF is the tolerance factor of the sense resistor. PCB Layout Considerations Layout is critical to reduce noises and ensure specified per- formance. The important guidelines are listed as follows: 1. Minimize the parasitic inductance in the loop of input ca- pacitors and MOSFETS: Q1, Q2 by using wide and short traces. This is important because the rapidly switching current, together with wiring inductance can generate large voltage spikes which can cause noise problems. 2. Always minimize the high-current ground traces: such as the traces from PGND pin to the source of Q2, then to the negative terminals of the output capacitors. 3. Use dedicated (Kelvin sense) and short traces from CSH, CSL pins to the sense resistor, R3. Keep these traces away from noise traces (such as SW trace, and gate traces). 4. Minimize the traces connecting Q2 and the Schottky di- ode. Any parasitic inductance in the loop can delay the turn-on of the Schottky diode, which diminishes the effi- ciency gain from adding D1. 5. Minimize the traces from drivers (HDRV pin and LDRV pin) to the MOSFETs gates. 6. Minimize the trace from the center of the output resistor divider to the FB pin and keep it away from noise sources to avoid noise pickup. A dedicated sense trace (separated from the power trace) can be used to con- nect the top of the resistor divider to the output. The sense trace ensures tight regulation at the output. Application Circuits A typical application circuit is shown in Figure 2, with some of the components values shown in Table 1. www.national.com 9 |
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