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8T74S208C-01NLGI 데이터시트(PDF) 8 Page - Integrated Device Technology

부품명 8T74S208C-01NLGI
상세설명  2.5 V Differential LVDS Clock Divider and Fanout Buffer
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
August 22, 2016
8T74S208C-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Typical Phase Jitter at 156.25MHz
Offset from Carrier Frequency (Hz)
Additive Phase: 96fs (typical)
The input source is 156.25MHz Wenzel Oscillator.


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