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TSB81BA3I 데이터시트(PDF) 3 Page - Texas Instruments

부품명 TSB81BA3I
상세설명  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
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홈페이지  http://www.ti.com
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TSB81BA3, TSB81BA3I
IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER
SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators
to monitor the line states during initialization and arbitration when connected to a 1394a−2000 compliant device.
The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA
channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used
during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel
monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied
twisted pair bias (TPBIAS) voltage.
When connected to a 1394a−2000 compliant node, the TSB81BA3 provides a 1.86-V nominal bias voltage at
the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each
port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an external filter capacitor of 1
µF.
The line drivers in the TSB81BA3, are designed to work with external 112-
Ω termination resistor networks in
order to match the 110-
Ω cable impedance. One termination network is required at each end of a twisted-pair
cable. Each network is composed of a pair of series-connected ~56-
Ω resistors. The midpoint of the pair of
resistors that are connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal.
The midpoint of the pair of resistors that are directly connected to the TPB terminals is coupled to ground through
a parallel RC network with recommended values of 5 k
Ω and 270 pF. The values of the external line-termination
resistors are designed to meet the standard specifications when connected in parallel with the internal receiver
circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current,
along with other internal operating currents.
When the power supply of the TSB81BA3 is off while the twisted-pair cables are connected, the TSB81BA3
transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at
the other end of the cable.
When the TSB81BA3 is used without one or more of the ports brought out to a connector, the twisted-pair
terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must
be forced to the 1394a-only mode (Data-Strobe-only mode), then the TPB+ and TPB− terminals can be tied
together and then pulled to ground; or the TPB+ and TPB− terminals can be connected to the suggested normal
termination network. The TPA+ and TPA− terminals of an unused port can be left unconnected. The TPBIAS
terminal can be connected to a 1-
µF capacitor to ground or left unconnected.
To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2)
needs to be pulled to ground through a 1-k
Ω resistor. The port must be operated in the 1394b bilingual mode
whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a
1394a-only port, the force data-strobe-only terminal (DS0, DS1, or DS2) needs to be pulled to 3.3 V VCC through
a 1-k
Ω resistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected
to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b
signalling is never sent across a 1394a cable.
The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For
normal operation, the TESTM and TESTW terminals must be connected to VDD through a 1-kΩ resistor. The
SE and SM terminals must be tied to ground through a 1-k
Ω resistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the
self-ID packet. They may be pulled high through a 1-k
Ω resistor or hardwired low as a function of the equipment
design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for
power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set
indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager
(BM). On the TSB81BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a
contender for IRM or BM, then the node software must set this bit in the PHY register set.


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