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SST26VF064B 데이터시트(PDF) 8 Page - Microchip Technology |
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SST26VF064B 데이터시트(HTML) 8 Page - Microchip Technology |
8 / 85 page SST26VF064B / SST26VF064BA DS20005119G-page 8 2015 Microchip Technology Inc. The Write Block-Protection Register command is a two-cycle command which requires that Write-Enable (WREN) is executed prior to the Write Block-Protection Register command. The Global Block-Protection Unlock command clears all write protection bits in the Block-Protection register. 4.1.2 WRITE-PROTECTION LOCK-DOWN (VOLATILE) To prevent changes to the Block-Protection register, use the Lock-Down Block-Protection Register (LBPR) command to enable Write-Protection Lock-Down. Once Write-Protection Lock-Down is enabled, the Block-Protection register can not be changed. To avoid inadvertent lock down, the WREN command must be executed prior to the LBPR command. To reset Write-Protection Lock-Down, performing a power cycle on the device is required. The Write-Protection Lock-Down status may be read from the Status register. 4.1.3 WRITE-LOCK LOCK-DOWN (NON- VOLATILE) The non-Volatile Write-Lock Lock-Down register is an alternate register that permanently prevents changes to the block-protect bits. The non-Volatile Write-Lock Lock-Down register (nVWLDR) is 136 bits wide per device: one bit each for the eight 8-KByte parameter blocks, and one bit each for the remaining 32 KByte and 64 KByte overlay blocks. See Table 5-6 for address range protected per register bit. Writing ‘1’ to any or all of the nVWLDR bits disables the change mechanism for the corresponding Write-Lock bit in the BPR, and permanently sets this bit to a ‘1’ (protected) state. After this change, both bits will be set to ‘1’, regardless of the data entered in subsequent writes to either the nVWLDR or the BPR. Subsequent writes to the nVWLDR can only alter available locations that have not been previously written to a ‘1’. This method provides write-protection for the corresponding memory-array block by protecting it from future pro- gram or erase operations. Writing a ‘0’ in any location in the nVWLDR has no effect on either the nVWLDR or the corresponding Write-Lock bit in the BPR. Note that if the Block-Protection register had been pre- viously locked down, see “Write-Protection Lock-Down (Volatile)”, the device must be power cycled before using the nVWLDR. If the Block-Protection register is locked down and the Write nVWLDR command is accessed, the command will be ignored. 4.2 Hardware Write Protection The hardware Write Protection pin (WP#) is used in conjunction with the WPEN and IOC bits in the config- uration register to prohibit write operations to the Block- Protection and Configuration registers. The WP# pin function only works in SPI single-bit and dual-bit read mode when the IOC bit in the configuration register is set to ‘0’. The WP# pin function is disabled when the WPEN bit in the configuration register is ‘0’. This allows installa- tion of the SST26VF064B/064BA in a system with a grounded WP# pin while still enabling Write to the Block-Protection register. The Lock-Down function of the Block-Protection Register supersedes the WP# pin, see Table 4-1 for Write Protection Lock-Down states. The factory default setting at power-up of the WPEN bit is ‘0’, disabling the Write Protect function of the WP# after power-up. WPEN is a non-volatile bit; once the bit is set to ‘1’, the Write Protect function of the WP# pin continues to be enabled after power-up. The WP# pin only protects the Block-Protection Register and Config- uration Register from changes. Therefore, if the WP# pin is set to low before or after a Program or Erase command, or while an internal Write is in progress, it will have no effect on the Write command. The IOC bit takes priority over the WPEN bit in the con- figuration register. When the IOC bit is ‘1’, the function of the WP# pin is disabled and the WPEN bit serves no function. When the IOC bit is ‘0’ and WPEN is ‘1’, set- ting the WP# pin active low prohibits Write operations to the Block Protection Register. |
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