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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SST25VF016B-50-4I-S2AE 데이터시트(PDF) 9 Page - Microchip Technology |
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SST25VF016B-50-4I-S2AE 데이터시트(HTML) 9 Page - Microchip Technology |
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9 / 30 page  2015 Microchip Technology Inc. DS20005044C-page 9 SST25VF016B 4.4.1 READ (25 MHZ) The Read instruction, 03H, supports up to 25 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automati- cally increment to the beginning (wrap-around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE# must remain active low for the duration of the Read cycle. See Figure 4-3 for the Read sequence. FIGURE 4-3: READ SEQUENCE 4.4.2 HIGH-SPEED-READ (50 MHZ) The High-Speed-Read instruction supporting up to 50 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 4-4 for the High- Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically incre- ment to the beginning (wrap-around) of the address space. Once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. FIGURE 4-4: HIGH-SPEED-READ SEQUENCE 1271 ReadSeq.0 CE# SO SI SCK ADD. 01 2 3 4 5 6 7 8 ADD. ADD. 03 HIGH IMPEDANCE 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 DOUT MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 1271 HSRdSeq.0 CE# SO SI SCK ADD. 012 34 5 6 7 8 ADD. ADD. 0B HIGH IMPEDANCE 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 X MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 80 71 72 DOUT Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH) |
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