전자부품 데이터시트 검색엔진 |
|
TPA3128D2DAP 데이터시트(PDF) 3 Page - Texas Instruments |
|
|
TPA3128D2DAP 데이터시트(HTML) 3 Page - Texas Instruments |
3 / 37 page 32 31 30 29 19 13 14 15 16 17 18 20 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 24 28 27 26 25 FAULTZ SDZ SYNC AM0 AM1 MUTE LINN LINP PLIMIT RINN GVDD RINP AVCC OUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSEL BSPR GND GND PVCC GND GAIN/SLV AM2 Thermal PAD 3 TPA3128D2 www.ti.com SLOS941A – MAY 2016 – REVISED DECEMBER 2016 Product Folder Links: TPA3128D2 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 5 Pin Configuration and Functions DAP Package 32-Pin HTSSOP With PowerPAD Down TPA3128D2, Top View (1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 MODSEL I Mode selection logic input (LOW = Ultra Low Idle Loss Mode, HIGH = BD Mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ DO General fault reporting including Over-temp, DC Detect. Open drain. FAULTZ = High, normal operation FAULTZ = Low, fault condition 4 RINP I Positive audio input for right channel. Connect to GND for MONO mode. 5 RINN I Negative audio input for right channel. Connect to GND for MONO mode. 6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. 8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider. 9 GND G Ground 10 LINP I Positive audio input for left channel. Connect to GND for PBTL mode. 11 LINN I Negative audio input for left channel. Connect to GND for PBTL mode. 12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 AM2 I AM Avoidance Frequency Selection 14 AM1 I AM Avoidance Frequency Selection 15 AM0 I AM Avoidance Frequency Selection 16 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal. 17 AVCC P Analog Supply |
유사한 부품 번호 - TPA3128D2DAP |
|
유사한 설명 - TPA3128D2DAP |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |