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MC74VHC1GT08_13 데이터시트(Datasheet) 1 Page - ON Semiconductor

부품명 MC74VHC1GT08_13
상세내용  2-Input AND Gate/CMOS Logic Level Shifter
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제조사  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 12
1
Publication Order Number:
MC74VHC1GT08/D
MC74VHC1GT08
2-Input AND Gate/CMOS
Logic Level Shifter
The MC74VHC1GT08 is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT08 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT08 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 64; Equivalent Gates = 15
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
VCC
IN B
IN A
OUT Y
GND
IN A
IN B
OUT Y
&
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
1
2
34
5
PIN ASSIGNMENT
1
2
3
GND
IN B
IN A
4
5VCC
OUT Y
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
L
L
L
H
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
http://onsemi.com
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
1
5
1
5
1
5
VT M G
G
VT
= Device Code
M
= Date Code*
G
= Pb−Free Package
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)
1
5
VT M G
G




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