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X1243S8I 데이터시트(PDF) 4 Page - Xicor Inc.

부품명 X1243S8I
상세설명  Real Time Clock/Calendar/Alarm with EEPROM
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제조업체  XICOR [Xicor Inc.]
홈페이지  http://www.xicor.com
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X1243
4
disables the output IRQ for that alarm condition, but the
alarm condition can still be checked by polling the
alarm flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Range
76
5
4
3
2
1
0
(optional)
003F
Status
SR
BAT
AL1
AL0
0
0
RWEL
WEL
RTCF
0037
RTC
(SRAM)
Y2K
0
0
Y2K21
Y2K20
Y2K13
0
0
Y2K10
19/20
0036
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
0034
MO
0
0
0
G20
G13
G12
G11
G10
1-12
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
0032
HR
T24
0
H21
H20
H13
H12
H11
H10
0-23
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
0011
Control
(E2PROM)
INT
IM
AL1E
AL0E
0
0
0
0
0
00h
0010
BL
BP2
BP1
BP0
0
0
0
0
0
00h
000F
Alarm1
(E2PROM)
unused
000E
DWA1
EDW1
0
0
0
0
DY2
DY1
DY0
0-6
0h
000D
YRA1
Unused - Default = RTC Year value
000C
MOA1
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
0h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
0h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
0h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
0h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
0h
0007
Alarm0
(E2PROM)
unused
0006
DWA1
EDW0
0
0
0
0
DY2
DY1
DY0
0-6
0h
0005
YRA0
Unused - Default = RTC Year value
0004
MOA0
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
0h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
0h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
0h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
0h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
0h
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
The X1243 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical


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