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Si513 데이터시트(PDF) 11 Page - Silicon Laboratories |
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Si513 데이터시트(HTML) 11 Page - Silicon Laboratories |
11 / 20 page Si512/513 Rev. 1.0 11 2. Pin Descriptions *Note: Supports integrated 1:2 CMOS buffer. See section 2.1 “2.1. Dual CMOS Buffer” and section 3 “3. Ordering Information”. Table 11. Si512 Pin Descriptions (CMOS, OE Pin 2) Pin Name CMOS Function 1 FS Frequency Selected. 0 = First frequency selected. 1 = Second frequency selected. 2 OE Output Enable. Internal pull-up for OE active high. Pull- down for OE active low. See ordering information. 3 GND Electrical and Case Ground. 4 CLK Clock Output. 5 NC No connect. Make no external connection to this pin. 6 VDD Power Supply Voltage. Table 12. Si513 Pin Descriptions (CMOS, OE Pin 1) Pin Name CMOS Function 1 OE Output Enable. Internal pull-up for OE active high. Pull- down for OE active low. See ordering information. 2 FS Frequency Selected. 0 = First frequency selected. 1 = Second frequency selected. 3 GND Electrical and Case Ground. 4 CLK Clock Output. 5 NC No connect. Make no external connection to this pin. 6 VDD Power Supply Voltage. Table 13. Si512 Pin Descriptions (OE Pin 2) Pin Name LVPECL/LVDS/HCSL/Dual CMOS Function 1 FS Frequency Selected. 0 = First frequency selected. 1 = Second frequency selected. 2 OE Output Enable. Internal pull-up for OE active high. Pull- down for OE active low. See ordering information. 3 GND Electrical and Case Ground. 4 CLK+ Clock Output. 5 CLK– Complementary Clock Output. 6 VDD Power Supply Voltage. Si512 CMOS Si512 LVDS/LVPECL/ HCSL/ Dual CMOS* Si513 LVDS/LVPECL/ HCSL/Dual CMOS* 1 2 3 6 5 4 GND OE VDD CLK+ CLK– FS 1 2 3 6 5 4 GND OE VDD CLK NC FS 1 2 3 6 5 4 GND FS VDD CLK+ CLK– OE Si513 CMOS 1 2 3 6 5 4 GND FS VDD CLK NC OE |
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