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SI52131-A11A 데이터시트(PDF) 1 Page - Silicon Laboratories |
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SI52131-A11A 데이터시트(HTML) 1 Page - Silicon Laboratories |
1 / 19 page Rev 1.0 3/13 Copyright © 2013 by Silicon Laboratories Si52131-A11A Si52131-A11A PCI-E XPRESS G EN1, G EN2, & G EN3 TWO O UTPUT C LOCK G ENER- ATOR WITH 25 MH Z R EFERENCE C LOCK & A CTIVE L OW OE P INS Features Applications Description Si52131-A11A is a high-performance, PCIe clock generator that can source two PCIe clocks and a buffered 25 MHz reference clock from a 25 MHz crystal or clock input. The PCIe clock outputs are compliant to PCIe Gen 1, Gen 2, and Gen 3 specifications. The device has three active low output enable pins for enabling and disabling each output. The device features two input select pins for frequency selection and spread control. The small footprint and low power consumption makes Si52131- A11A the ideal clock solution for consumer and embedded applications. Functional Block Diagram PCI-Express Gen1, Gen2 & Gen3 Compliant Supports Serial ATA (SATA) at 100 MHz Low power differential output buffers No termination resistors required Dedicated active low output enable pins for each output Pin selectable spread control Selectable frequencies: 100, 125, and 200 MHz Up two PCI-Express clocks 25 MHz reference clock 25 MHz Crystal Input or Clock input I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Extended Temperature –40 to 85oC 3.3 V Power supply 24-pin QFN package Network Attached Storage Multi-function Printer Ideal for Thunderbolt applications Wireless Access Point Routers Control RAM Control & Memory XIN/CLKIN XOUT SCLK SDATA SSC [1:0] OE#_DIFF [1:0] DIFF0 DIFF1 25MHz PLL1 (SSC) OE#_REF Divider Patents pending Ordering Information: See page 17 Pin Assignments VDD_REF REF OE_REF 1 VSS_REF VDD_DIFF OE_DIFF0 1 1 2 3 4 5 6 24 23 22 21 20 19 7 8 9 10 11 12 18 17 16 15 14 13 25 GND OE_DIFF1 1 VDD_DIFF DIFF1 DIFF1 DIFF0 DIFF0 Note 1. Internal 100 k-ohm pull-down resistor |
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