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Si82390CB-IS1 데이터시트(PDF) 11 Page - Silicon Laboratories

부품명 Si82390CB-IS1
상세설명  Enhanced output UVLO safety
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제조업체  SILABS [Silicon Laboratories]
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Equation 2 can be rearranged to determine the maximum package power dissipation for a given ambient temperature.
PDmax =
(Tjmax −TA
θ ja
)
Note: Where:
• PDmax is the maximum allowed power dissipation (W)
• Tjmax is the maximum allowed junction temperature (150 °C from table 4.8)
• TA is the ambient temperature (25 °C in this example)
• Θja is the thermal resistance of the package (100 °C/W from table 4.7)
PDmax = 1.25 W
Substituting values used in this example back into Equation 1, establishes a relationship between the maximum capacitive load and
switching frequency.
The following figure shows the relationship between the capacitive load and the switching frequency for four different driver supply vol-
tages. In the figure, the points along the load line represent the package dissipation-limited value of CL as a function of switching fre-
quency.
Figure 2.15. Max Load vs. Switching Frequency
2.5 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si8239x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si8239x as close to the device it is driving as possible. In addition, the VDD supply and
ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground
plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise
performance.
2.6 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 2.16 Si82391/2/3/6/8 Device Behavior during Nor-
mal Operation and Shutdown on page 11, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respective-
ly. Note that outputs VOA and VOB default low when input side power supply (VDDI) is not present.
2.6.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs VIA and VIB.
Si8239x Data Sheet
System Overview
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 10


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