74LVCH16374APAG8 datasheet(4/6 Pages) IDT

부품명	74LVCH16374APAG8

상세설명	3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP

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제조업체	IDT [Integrated Device Technology]

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INDUSTRIALTEMPERATURERANGE

4

IDT74LVCH16374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

TestConditions(1)

Min.

Max.

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

VCC – 0.2

—

V

VCC = 2.3V

IOH = – 6mA

2

—

VCC = 2.3V

IOH = – 12mA

1.7

—

VCC = 2.7V

2.2

—

VCC = 3V

2.4

—

VCC = 3V

IOH = – 24mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

IOL = 0.1mA

—

0.2

V

VCC = 2.3V

IOL = 6mA

—

0.4

IOL = 12mA

—

0.7

VCC = 2.7V

IOL = 12mA

—

0.4

VCC = 3V

IOL = 24mA

—

0.55

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperFlip-FlopOutputsenabled

CL = 0pF, f = 10Mhz

58

pF

CPD

PowerDissipationCapacitanceperFlip-FlopOutputsdisabled

24

SWITCHING CHARACTERISTICS(1)

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

fMAX

150

—

150

—

MHz

tPLH

PropagationDelay

—

4.9

1.5

4.5

ns

tPHL

xCLK to xQx

tPZH

OutputEnableTime

—

5.3

1.5

4.6

ns

tPZL

xOE to xQx

tPHZ

OutputDisableTime

—

6.1

1.5

5.5

ns

tPLZ

xOE to xQx

tSU

Set-up Time HIGH or LOW, data before CLK

↑

1.9

—

1.9

—

ns

tH

Hold Time HIGH or LOW, data after CLK

↑

1.1

—

1.1

—

ns

tW

Pulse duration, CLK HIGH or LOW

3.3

—

3.3

—

ns

tSK(o)

OutputSkew(2)

——

—

500

ps

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

유사한 부품 번호 - 74LVCH16374APAG8

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Renesas Technology Corp	74LVCH16374APAG8	399Kb / 7P	3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD OCTOBER 2015

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74LVCH16374APAG8 데이터시트(PDF) 4 Page - Integrated Device Technology

74LVCH16374APAG8 데이터시트(HTML) 4 Page - Integrated Device Technology

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