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AD9142ABCPZ 데이터시트(PDF) 10 Page - Analog Devices

부품명 AD9142ABCPZ
상세설명  Multiple chip synchronization
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Data Sheet
AD9142A
DAC LATENCY SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless
otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
WORD INTERFACE MODE
Fine/coarse modulation, inverse sinc, gain/phase compensation off
2× Interpolation
134
DACCLK cycles
4× Interpolation
244
DACCLK cycles
8× Interpolation
481
DACCLK cycles
BYTE INTERFACE MODE
Fine/coarse modulation, inverse sinc, gain/phase compensation off
2× Interpolation
145
DACCLK cycles
4× Interpolation
271
DACCLK cycles
8× Interpolation
506
DACCLK cycles
INDIVIDUAL FUNCTION BLOCKS
Modulation
Fine
17
DACCLK cycles
Coarse
10
DACCLK cycles
Inverse Sinc
20
DACCLK cycles
Phase Compensation
12
DACCLK cycles
Gain Compensation
16
DACCLK cycles
LATENCY VARIATION SPECIFICATIONS
Table 4.
Parameter
Min
Typ
Max
Unit
DAC LATENCY VARIATION1
SYNC Off
1
2
DACCLK cycles
SYNC On
0
1
DACCLK cycles
1
DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142A until the analog output begins to change.
Rev. A | Page 9 of 72


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