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AD7478AAKS-REEL 데이터시트(PDF) 7 Page - Analog Devices |
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AD7478AAKS-REEL 데이터시트(HTML) 7 Page - Analog Devices |
7 / 24 page REV. C AD7476A/AD7477A/AD7478A –7– Timing Example 1 Having fSCLK = 20 MHz and a throughput of 1 MSPS gives a cycle time of t2 + 12.5 (1/fSCLK) + tACQ = 1 µs. With t 2 = 10 ns min, this leaves tACQ to be 365 ns. This 365 ns satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ is comprised of 2.5 (1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This allows a value of 204 ns for tQUIET, satisfying the minimum requirement of 50 ns. CS SCLK SDATA t2 t6 t3 t4 t7 t5 t8 tCONVERT tQUIET ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0 B THREE-STATE THREE- STATE Z 4 LEADING ZEROS 12 345 13 14 15 16 t1 Figure 2. AD7476A Serial Interface Timing Diagram CS SCLK t2 tCONVERT B 1 234 5 13 14 15 16 C t8 tQUIET tACQ 12.5(1/fSCLK) 1/THROUGHPUT Figure 3. Serial Interface Timing Example Timing Example 2 Having fSCLK = 5 MHz and a throughput of 315 kSPS gives a cycle time of t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs. With t 2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ is comprised of 2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This allows a value of 128 ns for tQUIET, satisfying the minimum requirement of 50 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In Example 2, the signal should be fully acquired at approximately Point C in Figure 3. |
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