CS4122

http://onsemi.com

4

PIN FUNCTION DESCRIPTION

PIN #

PIN SYMBOL

FUNCTION

1

SCLK

Serial clock for shifting in/out of data. Rising edge shifts data on SI into the shift register and the falling

edge changes the data on SO.

2

CS

When High, allows data at SI to be shifted into the internal shift register with the rising edge of SCLK.

The falling edge transfers the shift register contents into the DAC and multiplexer to update the output

buffers. The falling edge also re−enables the output drivers if they have been disabled by a fault.

3

SIN−

Negative output for SINE coil.

4

SIN+

Positive output for SINE coil.

5, 6, 7, 8,

17, 18, 19, 20

GND

internally generated heat from the package and as such should be soldered to as large a PCB area as

possible.

9

10

C1+

Positive output for the #1 minor coil.

11

C1−

Negative output for the #1 minor coil.

12

5.0 V logic supply. The internal registers and latches are reset by a POR generated by the rising edge of

the voltage on this lead.

13

FAULT

Open−drain fault flag. A logic low on this lead indicates that an output is shorted or the device is in

thermal shutdown.

14

Analog supply. Nominally 12 V.

15

C2+

Positive output for the #2 minor coil.

16

C2−

Negative output for the #2 minor coil.

21

COS−

Negative output for COSINE coil.

22

COS+

Positive output for COSINE coil.

23

SI

Serial data input. Data present at the rising edge of the clock signal is shifted into the internal

shift register.

24

SO

Serial data output. Existing 12 bit data is shifted out when new data is shifted in. Allows cascading of

multiple devices on common serial port.