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ESDALC6V1P6 데이터시트(PDF) 4 Page - STMicroelectronics |
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ESDALC6V1P6 데이터시트(HTML) 4 Page - STMicroelectronics |
4 / 10 page ESDALC6V1P6 4/10 ® TECHNICAL INFORMATION 1. ESD protection by ESDALC6V1P6 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, ESDALC6V1P6 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDALC6V1P6. ESDALC6V1P6 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor. Fig. A2: ESD clamping behavior. To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis: we have: The results of the calculation done VG = 8kV, RG = 330Ω (IEC61000-4-2 standard), VBR = 6.4V (typ.) and Rd = 1.5Ω (typ.) give: This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side. Rd RG VG VBR VCL = V +R x I BR d PP VBR IPP VCL V(i/o) Device to be protected ESD surge ESDALC6V1P6 V I IPP RLOAD 1 Rd slope = R G R d""and""Rload R d > > Vi o ⁄ () V BR R d + V G R G -------- × = Vi o ⁄ () 42.8 Volts = Fig. A: Application example. IC to be protected I/O2 I/O1 I/O4 I/O3 |
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