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74LVX125MTR 데이터시트(PDF) 1 Page - STMicroelectronics |
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74LVX125MTR 데이터시트(HTML) 1 Page - STMicroelectronics |
1 / 12 page 1/12 August 2004 s HIGH SPEED: tPD=4.4ns (TYP.) at VCC = 3.3V s 5V TOLERANT INPUTS s POWER-DOWN PROTECTION ON INPUTS s INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V s LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C s LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVX125 is a low voltage CMOS QUAD BUS BUFFERs fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. This device requires the 3-STATE control input G to be set high to place the output into the high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVX125 LOW VOLTAGE QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LVX125MTR TSSOP 74LVX125TTR TSSOP SOP Rev. 3 |
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