ADF4007BCP-REEL datasheet(3/16 Pages) AD

부품명	ADF4007BCP-REEL

상세설명	High Frequency Divider/PLL Synthesizer

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ADF4007

Rev. 0 | Page 3 of 16

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,

TA = TMAX to TMIN, unless otherwise noted.

Table 1.

Parameter

B Version1

Unit

Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN)

1.0/7.0

GHz min/max

RF input level: +5 dBm to −10 dBm

RF Input Frequency

0.5/7.5

GHz min/max

RF input level: +5 dBm to −5 dBm

For lower frequencies, ensure that slew rate (SR) > 560 V/µs

REFIN CHARACTERISTICS

REFIN Input Sensitivity

0.8/VDD

V p-p min/max

Biased at AVDD/22

REFIN Input Frequency

20/240

MHz min/max

For f < 20 MHz, use square wave (slew rate > 50 V/µs)

REFIN Input Capacitance

10

pF max

REFIN Input Current

±100

µA max

PHASE DETECTOR

Phase Detector Frequency3

120

MHz max

MUXOUT

MUXOUT Frequency3

200

MHz max

CL = 15 pF

CHARGE PUMP

ICP Sink/Source

5.0

mA typ

With RSET = 5.1 kΩ

Absolute Accuracy

2.5

% typ

With RSET = 5.1 kΩ

RSET Range

3.0/11

kΩ typ

ICP Three-State Leakage

10

nA max

TA = 85°C

Sink and Source Current Matching

2

% typ

0.5 V

≤ VCP ≤ VP − 0.5 V

ICP vs. VCP

1.5

% typ

0.5 V

≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature

2

% typ

VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage

1.4

V min

VIL, Input Low Voltage

0.6

V max

IINH, IINL, Input Current

±1

µA max

TA = 25°C

CIN, Input Capacitance

10

pF max

LOGIC OUTPUTS

VOH, Output High Voltage

VDD − 0.4

V min

IOH = 100 µA

VOL, Output Low Voltage

0.4

V max

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7/3.3

V min/max

DVDD

AVDD

VP

AVDD/5.5

V min/max

AVDD

≤ VP ≤ 5.5 V

IDD4 (AIDD

DD

+ DI )

17

mA max

15 mA typ

IP

2.0

mA max

TA = 25°C

NOISE CHARACTERISTICS

Normalized Phase Noise Floor5

−219

dBc/Hz typ

1 Operating temperature range (B version) is −40°C to +85°C.

2 AC coupling ensures AVDD/2 bias. See

for typical circuit.

Figure 13

3 Guaranteed by design. Characterized to ensure compliance.

4 TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz.

5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider

value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.

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