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AM29LV642D 데이터시트(Datasheet) 3 Page - Advanced Micro Devices

부품명 AM29LV642D
상세내용  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
PDF  53 Pages
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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Am29LV642D
P R E L I M I NARY
GENERAL DESCRIPTION
The Am29LV642D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory device organized
as two Am29LV640D dice in a single 64-ball Fortified
BGA package. Each Am29LV640D is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
device organized as 4,194,304 words. Data appears
on DQ0-DQ15. The device is designed to be pro-
grammed in-system with the standard system 3.0 volt
V
CC supply. A 12.0 volt VPP is not required for program
or erase operations. The Am29LV642D is equipped
with two CE# pins for flexible selection between the
two internal 64 Mb devices. The device can also be
programmed in standard EPROM programmers.
The Am29LV642D offers access times of 90 and 120
ns and is offered in a 64-ball Fortified BGA package.
To eliminate bus contention the Am29LV642D device
has two separate chip enables (CE# and CE2#). Each
chip enable (CE# or CE2#) is connected to only one of
the two dice in the Am29LV642D package. To the
system, this device will be the same as two inde-
pendent Am29LV640D on the same board. The
only difference is that they are now packaged to-
gether to reduce board space.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
p re pro grams the arra y (if it is n ot a lre ad y pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The VersatileI/O™ (V
IO) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the V
IO pin. This allows the device to operate in 1.8
V, 3 V, or 5 V system environment as required. For
voltage levels below 3 V, contact an AMD representa-
tive for more information.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.




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