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AM29LV033C-70WDE 데이터시트(PDF) 10 Page - Advanced Micro Devices

부품명 AM29LV033C-70WDE
상세설명  32 Megabit (4 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

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Am29LV033C
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29LV033C Device Bus Operations
Legend:
L = Logic Low = V
IL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. When the ACC pin is at V
HH, the device enters the accelerated program mode. See “Accelerated Program Operations” for
more information.
2.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
Operation
CE#
OE#
WE#
RESET#
Addresses
DQ0–DQ7
Read
L
L
H
H
A
IN
D
OUT
Write (Note 1)
L
H
L
H
A
IN
D
IN
Standby
V
CC ±
0.3 V
XX
V
CC ±
0.3 V
X
High-Z
Output Disable
L
H
H
H
X
High-Z
Reset
X
X
X
L
X
High-Z
Sector/Sector Block Protect
(Note 2)
LH
L
V
ID
Sector Addresses,
A6 = L, A1 = H, A0 = L
D
IN, DOUT
Sector/Sector Block Unprotect
(Note 2)
LH
L
V
ID
Sector Addresses
A6 = H, A1 = H, A0 = L
D
IN, DOUT
Temporary Sector/Sector Block
Unprotect
XX
X
V
ID
A
IN
D
IN


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