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AK7755EN 데이터시트(PDF) 57 Page - Asahi Kasei Microsystems |
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AK7755EN 데이터시트(HTML) 57 Page - Asahi Kasei Microsystems |
57 / 109 page [AK7755] 014006643-E-00 2014/10 - 57 - 4. Clock Reset Clock reset is defined as when CKRESERN bit (CONT01: D0) = “0” after power-down release (PDN pin = “H”). The AK7755 is in the clock reset state after releasing power-down. At this time, all internal blocks of the AK7755, except the REF circuit and the power supply circuit for digital block, are in power-down mode. Even the PLL for internal master clock generation is not in operation. Control register write/read should be made 1ms (min.) after power-down release. Clock generating control registers (CONT00 ~ CONT01) must be set during clock reset. AINE bit (CONT00: D3) should be set to “1” first when using the IN1/INP1, IN2/INN1, IN3/INP2 and IN4/INN2 pins as analog inputs. DSP program and coefficient RAM data writing to the DSP become available in 1ms by setting DLRDY bit (CONT0F: D0) = “0” → “1” during clock reset (CKRESETN bit = “0”). DLRDY bit must be set to “0” when finishing downloading. Necessary system clock (XTI@CKM mode0-2 or BICK@CKM mode 3, 5(CONT00: D6-D4)) must be input before releasing the clock reset (Figure 16). The PLL for internal master clock starts operation and generating master clock when the clock reset state is released (CKRESETN bit = “1”). Do not send DSP programs, coefficient data or a command code for system reset release from a microcontroller to the AK7755 until the PLL oscillation is stabilized (for 10ms or during Low output period of the PLLLOCK signal from the STO pin). System clocks must be changed during a clock reset or in power-down mode (PDN pin = “L”). The AK7755 enters clock reset state by setting CKRESETN bit to “0” after system reset. The PLL and the internal clock are stopped by this clock reset and the clock change can be done safely. Change register settings and system clock frequencies during the clock reset. After a system clock is stabilized, the PLL starts operation by setting CKRESETN bit to “1”. CSN SCLK (Simplified) SI 0xCF 0x00 0xCF 0x0C Command Code & DSP Program Transmitting Period 0xC1 0x00 CKRESETN Input Clock Changeable Period 0xC1 0x01 PLL Stable Oscillation XTI BICK CKM mode0 CKM mode3 CRESETN / DSPRESETN 0xC0 0x3x Figure 30. Clock Reset Sequence (e.g. CKM mode0 → CKM mode 3) |
유사한 부품 번호 - AK7755EN_16 |
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유사한 설명 - AK7755EN_16 |
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