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LSM330D 데이터시트(PDF) 33 Page - STMicroelectronics

부품명 LSM330D
상세설명  Low power mode
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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LSM330D
Digital interfaces
Doc ID 022562 Rev 2
33/66
6.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits, and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded in the LSM330D behaves like a slave device and the following protocol
must be adhered to. After the start condition (ST), a slave address is sent. Once a slave
acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7
LSb represent the actual register address while the MSb enables address auto increment. If
the MSb of the SUB field is ‘1’, the SUB (register address) will be automatically increased to
allow multiple data read/write.
Data is transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of
bytes sent per transfer is unlimited. Data is transferred with the most significant bit (MSb)
first. If a receiver cannot receive another complete byte of data until it has performed some
other function, it can hold the clock line, SCL, LOW to force the transmitter into a wait state.
Table 12.
Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
SAK
SAK
Table 13.
Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
DATA
DATA
SP
Slave
SAK
SAK
SAK
SAK
Table 14.
Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
SAK
SAK
DATA
Table 15.
Transfer when master is receiving (reading) multiple bytes of data from slave
Master
ST SAD+W
SUB
SR SAD+R
MAK
MAK
NMAK
SP
Slave
SAK
SAK
SAK
DATA
DATA
DATA


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