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LSM330D 데이터시트(PDF) 49 Page - STMicroelectronics

부품명 LSM330D
상세설명  Low power mode
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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LSM330D 데이터시트(HTML) 49 Page - STMicroelectronics

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LSM330D
Register descriptions
Doc ID 022562 Rev 2
49/66
Interrupt 1 source register. Read only register.
Reading at this address clears INT1_SRC_A IA bit (and the interrupt signal on INT 1 pin)
and allows the refreshing of the data in the INT1_SRC_A register if the latched option was
chosen.
8.16
INT1_THS_A (32h)
8.17
INT1_DURATION_A (33h)
D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
YH
Y high. Default value: 0
(0: no interrupt, 1: Y High event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y Low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X High event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X Low event has occurred)
Table 46.
INT1_SRC_A description (continued)
Table 47.
INT1_THS_A register
0(1)
1.
This bit has to be set ‘0’ for correct operation.
THS6
THS5
THS4
THS3
THS2
THS1
THS0
Table 48.
INT1_THS_A description
THS6 - THS0
Interrupt 1 threshold. Default value: 000 0000
Table 49.
INT1_DURATION_A register
0(1)
1.
This bit must be set ‘0’ for correct operation.
D6
D5
D4
D3
D2
D1
D0
Table 50.
INT1_DURATION_A description
D6 - D0
Duration value. Default value: 000 0000


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