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M41T315V-85MQ6F 데이터시트(PDF) 7 Page - STMicroelectronics |
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M41T315V-85MQ6F 데이터시트(HTML) 7 Page - STMicroelectronics |
7 / 24 page 7/24 M41T315Y*, M41T315V, M41T315W OPERATION Figure 6., page 5 illustrates the main elements of the device. The following paragraphs describe the signals and functions. Communication with the clock is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecu- tive WRITE cycles containing the proper data on data in (D). All accesses which occur prior to rec- ognition of the 64-bit pattern are directed to mem- ory via the chip enable output pin (CEO). After recognition is established, the next 64 READ or WRITE Cycles either extract or update data in the clock and CEO remains high during this time, disabling the connected memory (see Table 2., page 7). Data transfer to and from the timekeeping function is accomplished with a serial bit stream under con- trol of chip enable input (CEI), output enable (OE), and WRITE enable (WE). Initially, a READ cycle using the CEI and OE control of the clock starts the pattern recognition sequence by moving the point- er to the first bit of the 64-bit comparison register. Next, 64 consecutive WRITE cycles are executed using the CEI and WE control of the clock. These 64 WRITE cycles are used only to gain access to the clock. When the first WRITE cycle is executed, it is com- pared to the first bit of the 64-bit comparison reg- ister. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not ad- vance and all subsequent WRITE cycles are ig- nored. If a READ cycle occurs at any time during pattern recognition, the present sequence is abort- ed and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all the bits in the comparison register have been matched (see Figure 10., page 11.) With a correct match for 64 bits, access to the reg- isters is enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles will cause the device to either receive data on D, or transmit data on Q, depending on the lev- el of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recogni- tion sequence or data transfer sequence to the de- vice. For a SO16 pin package, a standard 32.768 kHz quartz crystal can be directly connected to the M41T315Y/V/W via pins 1 and 2 (XI, XO). The crystal selected for use should have a specified load capacitance (CL) of 12.5 pF (see Table 10., page 17). Table 2. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. Note: 1. See Table 11., page 17 for details. Mode VCC CEI OE WE D QPower Deselect 4.5 to 5.5V or 3.0 to 3.6V or 2.7 to 3.3V VIH X X Hi-Z Hi-Z Standby WRITE VIL X VIL DIN Hi-Z Active READ VIL VIL VIH Hi-Z DOUT Active READ VIL VIH VIH Hi-Z Hi-Z Active Deselect VSO to VPFD (min) (1) X X X Hi-Z Hi-Z CMOS Standby Deselect ≤ VSO(1) X X X Hi-Z Hi-Z Battery Back-up Mode |
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