CDCF2510

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS628D − APRIL 1999 − REVISED DECEMBER 2004

8

POST OFFICE BOX 655303

TYPICAL CHARACTERISTICS

Figure 6

STATIC PHASE ERROR

vs

CLOCK FREQUENCY

50

60

70

80

90

100 110

120

fc − Clock Frequency − MHz

−100

−150

−250

−300

−350

−400

−200

−50

0

−450

−500

VCC = 3.3 V

C(LY) = 25 pF

C(LF) = 12 pF

TA = 25°C

See Note A

130

140

Figure 7

300

250

200

0

50

60

70

80

90

100 110

120 130 140

150

100

50

Cycle to Cycle

Peak to Peak

fc − Clock Frequency − MHz

VCC = 3.3 V

C(LY) = 25 pF

C(LF) = 12 pF

TA = 25°C

See Notes A and B

JITTER

vs

CLOCK FREQUENCY

NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω

B. Phase error measured from CLK to FBIN

C. C(LY) = Lumped capacitive load at Y

D. C(LF) = Lumped feedback capacitance at FBIN

Figure 8

ANALOG SUPPLY CURRENT

vs

CLOCK FREQUENCY

12

10

6

4

2

0

8

10

30

50

70

90

110

130

150

14

16

AVCC = VCC = 3.465 V

Bias = 0/3 V

C(LY) = 25 pF

C(LF) = 0

TA = 25°C

See Notes A and B

fc − Clock Frequency − MHz

Figure 9

SUPPLY CURRENT

vs

CLOCK FREQUENCY

250

150

100

50

0

200

10

30

50

70

90

110

130

150

fc − Clock Frequency − MHz

300

AVCC = VCC = 3.465 V

Bias = 0/3 V

C(LY) = 25 pF

C(LF) = 0

TA = 25°C

See Notes A and B

NOTES: A. C(LY) = Lumped capacitive load at Y

B. C(LF) = Lumped feedback capacitance at FBIN