전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

DAC5682ZIRGC 데이터시트(PDF) 6 Page - Texas Instruments

Click here to check the latest version.
부품명 DAC5682ZIRGC
상세설명  16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)
Download  66 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

DAC5682ZIRGC 데이터시트(HTML) 6 Page - Texas Instruments

Back Button DAC5682ZIRGC Datasheet HTML 2Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 3Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 4Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 5Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 6Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 7Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 8Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 9Page - Texas Instruments DAC5682ZIRGC Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 66 page
background image
DAC5682Z
SLLS853F – AUGUST 2007 – REVISED JANUARY 2015
www.ti.com
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
8, 12, 14,
LVDS negative input data bits 0 through 15. (See D[15:0]P description above)
16, 18, 20,
D15N is most significant data bit (MSB) – pin 8
22, 24, 28,
D0N is least significant data bit (LSB) – pin 43
D[15..0]N
I
30, 32, 34,
36, 38, 41,
43
LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately
DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit.
DCLKP
25
I
See DLL Operation. For proper external termination, connect a 100
Ω resistor across LVDS clock source
lines followed by series 0.01
μF capacitors connected to each of DCLKP and DCLKN pins (see ). For best
performance, the resistor and capacitors should be placed as close as possible to these pins.
DCLKN
26
I
LVDS negative input clock. (See the DCLKP description)
10, 39, 50,
Digital supply voltage. (1.8 V)
DVDD
I
63
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
EXTIO
56
I/O
Used as 1.2-V internal reference output when EXTLO = GND, requires a 0.1
μF decoupling capacitor to
AGND when used as reference output.
EXTLO
58
O
Connect to GND for internal reference, or AVDD for external reference.
4, Thermal
Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and
GND
I
Pad
IOVDD supplies.
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in
IOUTA1
52
O
a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear
on the IOUTA1/A2 pair only.
A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1
IOUTA2
53
O
described above. An input data value of 0x0000 results in a 0-mA sink and the most positive voltage on the
IOUTA2 pin.
IOUTB1
61
O
B-Channel DAC current output. See the IOUTA1 description above.
IOUTB2
60
O
B-Channel DAC complementary current output. See the IOUTA2 description above.
IOVDD
9
I
Digital I/O supply voltage (3.3 V) for pins RESETB, SCLK, SDENB, SDIO, SDO.
PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both
LPF
64
I
PLL_bypass and PLL_sleep control bits for reduced power dissipation.
RESETB
49
I
Resets the chip when low. Internal pullup.
SCLK
47
I
Serial interface clock. Internal pulldown.
SDENB
48
I
Active low serial data enable, always an input to the DAC5682Z. Internal pullup.
Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO
SDIO
46
I/O
pin is an input only. Internal pulldown.
Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state
SDO
45
O
in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14
SDO_func_sel(2:0). Internal pulldown.
LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100
Ω termination resistor. By
SYNCP
5
I
default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N
Operation paragraph for a detailed description.
SYNCN
6
I
LVDS SYNC negative input data.
Digital supply voltage. (1.8 V) Connect to DVDD pins for normal operation. This supply pin is also used
VFUSE
44
I
for factory fuse programming.
6
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: DAC5682Z


유사한 부품 번호 - DAC5682ZIRGC

제조업체부품명데이터시트상세설명
logo
Texas Instruments
DAC5682ZIRGC25 TI-DAC5682ZIRGC25 Datasheet
2Mb / 59P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5682ZIRGCR TI-DAC5682ZIRGCR Datasheet
2Mb / 56P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5682ZIRGCR TI-DAC5682ZIRGCR Datasheet
2Mb / 59P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5682ZIRGCRG4 TI-DAC5682ZIRGCRG4 Datasheet
2Mb / 59P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5682ZIRGCT TI-DAC5682ZIRGCT Datasheet
2Mb / 56P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
More results

유사한 설명 - DAC5682ZIRGC

제조업체부품명데이터시트상세설명
logo
Texas Instruments
DAC5682Z TI-DAC5682Z_09 Datasheet
2Mb / 59P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5682Z TI-DAC5682Z Datasheet
2Mb / 56P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5681Z TI-DAC5681Z_15 Datasheet
2Mb / 58P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5681Z TI-DAC5681Z Datasheet
379Kb / 8P
[Old version datasheet]   16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)
DAC5682Z TI-DAC5682Z_15 Datasheet
3Mb / 66P
[Old version datasheet]   DAC5682Z 16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)
DAC3282 TI-DAC3282 Datasheet
1Mb / 49P
[Old version datasheet]   16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)
DAC3282 TI-DAC3282_10 Datasheet
1Mb / 51P
[Old version datasheet]   16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)
DAC3282_101 TI-DAC3282_101 Datasheet
1Mb / 53P
[Old version datasheet]   16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)
DAC5681 TI-DAC5681_15 Datasheet
1Mb / 48P
[Old version datasheet]   16-BIT, 1.0 GSPS Digital-to-Analog Converter (DAC)
DAC5681 TI-DAC5681 Datasheet
1Mb / 47P
[Old version datasheet]   16-BIT, 1.0 GSPS DIGITAL-TO-ANALOG CONVERTER (DAC)
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com